The present invention relates to a method as well as a circuit for transmitting data from a system, which is operated by means of a first clock, to a system operated by means of a second clock, whereby the clock rate of the second clock is higher than the clock rate of the first clock.
When data is transmitted between systems, which are operated in different clock domains, in particular when data is transmitted from a system with a relatively low clock rate to a system with a relatively high clock rate, generally the problem arises of synchronizing the data transfer as accurately as possible, so that for example as a result of clock jitter no data is lost or duplicated. Furthermore it is important in particular for hardware filters that the data is transmitted equidistantly, that is to say at regular intervals or in the form of regular data packets, from the lower clock domain to the higher clock domain.
FIG. 3 depicts a synchronizing circuit in accordance with the prior art, which can be used for synchronizing the data transfer from a system operated by means of a relatively low clock rate CLK1 to a system operated by means of a relatively high clock rate CLK2.
As shown in FIG. 3, this synchronizing circuit on the input side comprises a shift register chain, in the present case with two registers 5, 6, whereby in the first register 5 the slower clock CLK1 is fed on the data input. The inverted output of the second register 6 is fed to an AND gate 9, which receives the output signal of the first register 5 as a further input signal. The output of the AND gate 9 is connected to the data input of a further register 8, at the output of which an enabling signal EN for a register 7 is picked up, whereby the data DIN to be transmitted lies on the data input of the register 7. All registers 5-8 are clocked with the faster clock rate CLK2. The logic circuit provided at the output of the shift register chain 5, 6 ensures that a rising clock edge of the slower clock CLK1 can be registered, whereby in this case an enabling pulse EN for the register 7 is produced, so that the data DIN lying on the data input of the register 7 are outputted with the faster clock rate CLK2 in the form of the data DOUT.
FIG. 4 depicts the time progression of the individual signals illustrated in FIG. 3, whereby the output signals REG0 or REG1 of the registers 5 or 6 are also represented in particular. As is evident from FIG. 4, the clock rate of the faster clock CLK2 is four times higher than the clock rate of the slower clock CLK1. In FIG. 4 the clock cycles or clock periods of the clock CLK2, which in each case lie within a clock cycle of the clock CLK1, are numbered with 0. . . 3.
As is equally evident from FIG. 4, the clock edges of the clock CLK1 can vary as a result of clock jitter in such a manner that no clock edge can be accurately recognized with the aid of the synchronizing circuit shown in FIG. 3 in a specific clock cycle of the clock CLK2. Due to the clock jitter of the slower clock CLK1 the rising clock edge of the clock CLK1 can for example be registered in the clock cycle No. 0 or however also only in the clock cycle No. 1 of the clock CLK2. In FIG. 4 the respective progression of the signals REG0, REG1, EN and DOUT consequently ensuing is illustrated for both cases, whereby case A represented in FIG. 4 corresponds to a registration of the rising clock edge of the clock CLK1 in the clock cycle No.0, while case B corresponds to a registration of the rising clock edge of the clock CLK1 in the clock cycle No. 1 of the clock CLK2.
In case A the rising clock edge of the slower clock CLK1 is already registered in the clock cycle No. 0 of the faster clock CLK2, which is evident from the progression of the output signal REG0 of the first register 5 in the shift register chain, so that the enabling signal EN is produced in the clock cycle No. 1. In case B however the enabling signal EN is only produced in the clock cycle No. 2 of the clock CLK2, whereby the data output is retarded accordingly.
The illustration in FIG. 4 demonstrates that sometimes as a result of clock jitter of the slower clock CLK1 the data cannot be transmitted equidistantly, since the enabling signal EN can arise in different clock cycles of the faster clock CLK2.
The object of the present invention is to propose a method as well as a device for transmitting data from a system operated by means of a first clock to a system operated by means of a second clock, whereby the clock rate of the second clock is higher than the clock rate of the first clock, as a result of which data can be transmitted equidistantly, that is to say regularly, even with unknown clock jitter and clock time misalignment.